This invention relates to addressing of pixels arranged in an array format for displaying applications, and more particularly to driving pixel address lines in a video display.
Addressable components that can be arranged in rows and columns are commonly found in applications ranging, e.g., from memory to panel video display devices. A matrix display apparatus for displaying video signals commonly comprises a display panel having an array of addressable components arranged in row and column lines of pixels. The two-dimensional row and column lines are usually arranged in a rectangular format. The addressable component is called a picture element, display element, or pixel, and consists of a light sensitive element. The display element may emit, reflect, or transmit light in response to signals addressed into the line. Display elements may be made from different materials and may be constructed in various ways depending on the type and use of the display device. Various types, such as liquid crystal cells, electrochromic cells, plasma cells, fluorescent display tubes, light-emitting diodes (LEDs), and electroluminescence cells have been known. Light modulating materials used to construct display elements have been well known in the industry, and they fundamentally depend on an applied electric field to modulate the amount of light emitted, reflected, or transmitted. Some of the light modulating materials do not exhibit sharp electric field versus light excitation characteristics. Thus, an active device such as a diode or transistor may be used in conjunction with the addressable components to improve the pixel light characteristics. For example, the use of a thin film MOS field effect transistor (TFT) as a switching element is well known to the artisans in the field.
The light output of the picture element may be proportional to the applied addressing signal in the matrix display. In order to address a specific picture element, or pixel, in a matrix display, the pixel must be identified and excited. The excited pixel will emit, reflect, or transmit light accordingly. The pixel in the latter case is being enabled. Within an array of a pixel matrix, each pixel may have a unique address that is specified in terms of row and column location, e.g., the element at row x, and column y, or element (x,y). To excite the pixel (x,y), so that to set it to the xe2x80x9conxe2x80x9d status, the pixel (x,y) is enabled by addressing the location (x,y) and exciting the pixel. The pixel may be excited by supplying a voltage above a threshold level to the addressed location.
In one addressing technique, the pixel (x,y) is electrically coupled to a row conductor which intersects with a column conductor. The pixel (x, y) is enabled by addressing the specific row conductor line x and the column conductor line y. Each line is addressed by a driving means, which addresses the line according to an applied signal. The driving means consists of a column driver circuit for each column operable according to the line frequency of an applied video signal for supplying data signals derived therefrom to the column in which the pixel is electrically coupled, a row driver circuit for each row for scanning the row in which the pixel is electrically coupled to, and a control circuit which controls the timing of operation of the driver circuits, which is responsive to an applied video signal.
All pixels arranged in a row line are electrically coupled to a row line and thus to a row driver. Pixels arranged in a column line are electrically coupled to a column line and thus to a column driver. Therefore, M pixels in one row are commonly coupled to a row driver, and each separately coupled to one of M column drivers. Similarly, N pixels in one column are commonly coupled to a column driver, and each separately coupled to one of N row drivers. A matrix display of Mxc3x97N pixels usually requires M column drivers and N row drivers, or M+N line drivers. Thus, a display with a resolution of 128xc3x971024 pixels consists of 1,310,720 pixels, 1280 columns of pixels and 1024 rows of pixels, and 2304 line drivers. Images are formed by enabling, or disabling, selected pixels in the pixel array usually in sequential manner from left to right and top to bottom.
FIG. 1 depicts a conventional video matrix display device 100 comprising a plurality of pixels P that are arranged along the y-axis in N rows driven by drivers RN and along the x-axis in M columns driven by drivers CM. Each pixel P has two connecting ports. The first port 122 of the pixel P1,1 is coupled to the row line 110a and the second port 112 of the pixel is coupled to the column line 120a. The first port of pixels P1,1 to P1,M are electrically coupled to row 110a, while the second ports are separately coupled to the corresponding columns driven by C1 to CM. For example, to enable pixel P3,4 row line 110c is addressed through driver R3, and column line 120d is simultaneously addressed through driver C4. A specific pattern of pixels may be addressed for enabling the pixels by activating a plurality of row and column drivers in a sequential manner. Thus, a large number of drivers are physically needed to construct a matrix display. The number of drivers increases with the increase in the display resolution since larger numbers of rows and columns are needed. A need therefore exists to reduce the number of drivers in a device using addressable components. For high-resolution displays, the cost of a large number of drivers may be significant to the overall cost of the display. The complexity of circuitry components associated with the drivers, such as signal generators, control units, and driver memory also increases with resolution, and further provides a disadvantage in addition to the large number of drivers. Reducing the number of needed drivers in matrix display devices, such as flat panel displays, while achieving or maintaining the same or better image resolution is desirable.
The problems identified above may be in large part solved by a matrix display method and apparatus that eliminates the large number of row and column line drivers needed to address and selectively enable addressable elements or pixels. To achieve the above advantage, an embodiment of the apparatus may provide a total of only two drivers to drive a Mxc3x97N display device, such as a flat panel display. A first and a second driver may be used to drive first and second signals at slightly different frequencies (or phase) on a first and a second display conductor. A plurality of pixels may be coupled between the first and second display conductors. The pixels may be addressed according to a pixel location in which the first signal may be approximately in phase with the second signal. The pixel location changes from one pixel to the next at a scan rate proportional to the difference between the first and second signal frequencies. The first and second conductors may contain a plurality of delay elements and tap-off points, wherein each pixel may be coupled between tap-off points on the first and second conductors. A plurality of pixel row and column conductors may be provided, each connected to a different tap-off point of the first and second display conductors.
The row and column conductors may be terminated by their characteristic impedance to prevent any reflection of the traveling signal. Further, the first and the second display conductors may also be terminated by their characteristic impedance to prevent any reflection of the signals traveling on any of the conductors. The periods of the first and second signals may be greater than or approximately equal to a propagation delay of between first and last tap-off points on the first and second conductors, respectively. The pulse width of the first and second signals may be less than or approximately equal to a propagation time of the first and second signal between adjacent tap-off points on the first and second display conductors, respectively. The matrix display pixels may be selectively enabled by modulating an amplitude of the first signal and an amplitude of the second signal when the selected pixel location(s) is addressed so that the voltage differential between the first and second signals is sufficient to enable the addressed pixel.
Broadly speaking, a method and apparatus are contemplated to selectively enable addressable elements in a Mxc3x97N array arrangement. The apparatus may comprise two separate display conductors driven by two separate drivers where the frequency of their signals is different. A plurality of addressable elements may be connected to tap-off points on the two display conductors. A plurality of row and column conductors may be connected to the first and second display conductors. Each row or column conductor may be connected into a single point on the display conductor and may be terminated by its characteristic impedance. The signals traveling on each display conductor may be sequentially delayed by delay elements. The pixels may be sequentially addressed at a rate proportional to the difference in frequency between the first and second signals, and may be selectively enabled according to the difference in amplitude between the first and second signals.
A pixel display is further contemplated comprising a sequence of pixels, each pixel coupled between a first display conductor and a separate second display conductor wherein a first driver and a second drivers drive a first signal and a second signal on the first and second display conductors, respectively. The pixels may be sequentially addressed at a rate proportional to the difference in frequency between the first and second signals, while they may be selectively activated according to the difference in amplitude between the first and second signals.
A method is further contemplated for driving an addressable elements array comprising driving a first signal on a first addressing conductor at a first frequency, and driving a second signal on a second addressing conductor at a second frequency. The second addressing conductor is separate from the first addressing conductor, and the first and second frequencies may be slightly different. The addressable elements may be sequentially addressed according to an addressable element location where the first signal is approximately in phase with the second signal. The activation of select addressable elements may be achieved by modulating the amplitudes of the first and second signals during the time when a pixel selected to be turned on is addressed so that the amplitude differential of the first and second signals may be sufficient to activate the selected addressable element.
For another solution, in a display comprising pixels arrayed in M rows and N columns, pixels in every row are coupled together by a row conductive element having first and second ends, and pixels in every column are coupled together by a column conductive element having first and second ends. The row-coupled pixels are driven by first and second row drivers (DX1, DX2) coupled respectively to the first and second ends of the row conductive element. The column-coupled pixels are driven by first and second column drivers (DY3, DY4) coupled respectively to the first and second ends of the column conductive element. Thus, a total of only four drivers is used to address Mxc3x97N elements in the array.
Each driver outputs a time-varying signal of a different frequency, and the driver signals propagate through the associated conductive element. The amplitude of any one driver is about half the total amplitude needed to activate or turn on a pixel. The time-varying voltage seen by a pixel in a row is determined by the amplitude and frequency (xcfx891, xcfx892) of row drivers DX1, DX2, and by the propagation time needed for the signals to reach the pixel. Similarly, column pixels see time-varying voltage signals determined by the amplitude and frequency (xcfx893, xcfx894) of column drivers DY3, DY4, and by the relevant propagation time.
One embodiment implements a pixel enabling signal using the beat-frequency difference between two driver source signals that propagate through a pixel string from opposite ends of the string. The driver difference signal dwells sufficiently long on each pixel location to deliver sufficient energy to turn the pixel on or off. Vertical scan rate is determined by frequency differential (xcfx891xe2x88x92xcfx892), and horizontal scan rate frequency differential (xcfx893xe2x88x92xcfx894). The absolute frequencies xcfx891,xcfx892,xcfx893,xcfx894 are set proportional to the propagation delay of the medium through which the signals from DX1, DX2, DY3, DY4 travel. Preferably the frequencies of the driver signals coupled to the same conductive element are approximately comparable to the inverse of the end-end propagation time associated with the conductive element. Video information to be displayed is used to modulate at least one of the row drivers and one of the column drivers.
In another embodiment, the columns may be addressed in parallel. Columns may be coupled to a display conductor by a charge transfer/isolation circuit. A voltage waveform or pulse train may be propagated down the display conductor such that a pulse is present on the display conductor for each pixel of a row of pixels to be addressed. When the beginning of the pulse train has propagated to the last column tap-off point so that a different pulse is present at each column tap-off point corresponding to the row of pixels to be selected, a corresponding charge is transferred to each column conductor in parallel. Thus, a voltage is supplied to turn each pixel on or off on the selected row as determined by the state of the pulse train at each column tap-off point. During the time the voltages are supplied to the column conductors, the column conductors are isolated from the column tap-off points so that a next pulse train corresponding to the next pixel row may be propagated down the display conductor. The rows may be selected by any row addressing technique, such as individual row drivers, or a beat-frequency technique employing only two row drivers.
In one embodiment, the charge transfer/isolation device for each column conductor comprises a diode with its anode connected to a column tap-off on the display conductor and its cathode connected to the column conductor. A capacitor may also be included. The anode of each capacitor may be connected to the column conductor and the cathodes connected to a load signal. The load signal may be driven to a low voltage to transfer charge to the capacitors according to the state of the pulse train at each tap-off point. The load signal may be driven to a high voltage to supply the charge to the column conductors. When the load signal is high, the diodes may be reversed biased or off to that the column conductors are isolated from the display conductor a the next row pulse train is propagated on the display conductor.
Other features and advantages of the invention will appear from the following description in which the preferred embodiments have been set forth in detail, in conjunction with the accompanying drawings.